1. Field of the Invention
The present invention relates generally to a capacitor sheet, a method for producing the same, a circuit board, and a semiconductor device, and particularly to a capacitor sheet having an improved structure suitable for mounting a semiconductor on a wiring board such as a mother board or a daughter board.
2. Related Background Art
Recently, the digitalization of circuits has been promoted in electronic apparatuses, which significantly accelerates higher-speed information processing, further size reduction, and the integration of a multiplicity of functions. This requires circuit boards to be capable of accommodating high-density circuit and mounting high-density component, so as to cope with an increase in the number of semiconductor components.
In response to the demand for high-density circuit accommodation, multilayer wiring boards having an inner via hole structure for all layers (“ALIVH” (a trademark of Matsushita Electric Industrial Co., Ltd.) structure), built-up wiring boards, etc., have been developed recently and put into practical application. Besides, as to the high-density component mounting, the technique of configuring semiconductor packages in the ball grid array (BGA) form or in the chip size package (CSP) form has been developed, whereby areas for mounting and spaces between components can be reduced considerably. Furthermore, to mount components at a further higher density, a technique of providing built-in by-pass capacitors indispensable for operations of a semiconductor inside a board, etc., has been developed.
For instance, JP 5(1993)-36857 A teaches an example in which by-pass capacitors, each of which is composed of a first conductive electrode layer, a second conductive electrode layer and a dielectric layer interposed between the foregoing two conductive electrode layers, are placed on a substrate made of silicon (Si), aluminum nitride (AlN), or the like, and a multilayer wiring layer composed of a wiring layer, an insulation layer, and the like is laminated further thereon. With this structure, semiconductor chips mounted on a surface of the lamination board and the by-pass capacitors incorporated therein are connected with each other through vias. Therefore, unlike a conventional configuration with surface-mounted chip capacitors, areas on which chip capacitors are mounted and wiring areas for connection are unnecessary on the surface of the board. This allegedly allows the degree of freedom in the arrangement of mounted components and the wiring to increase significantly, thereby allowing the high-density packaging to be implemented.
Recently, the frequencies of used signals also have been increased as integrated circuits such as ICs and LSIs have higher processing speeds and greater capacities. This leads to a problem in that switching noises generated in packages having integrated circuits built therein cause malfunctions.
In high-speed, large-capacity LSI packages conventionally used, multilayer structures in which power source layers and grounding layers are formed alternately is employed to maintain the electric characteristics thereof. Besides, a multiplicity of chip capacitors as decoupling capacitors are mounted in the vicinity of a LSI of the package board or a back face of the same.
On the other hand, there is a tendency to operate a CPU at a low voltage with large current to achieve lower power consumption, and this leads to a problem in that the power supply is insufficient upon the start-up of the CPU, thereby impairing the operability. In conventional cases, to stabilize the power supply upon the start-up, an electrolytic capacitor with a large capacity is provided in the vicinity of the LSI.
Thus, it is significantly effective to provide built-in capacitors inside a board so as to achieve high-density packaging. However, this results in a wiring layer being provided immediately under a face where a component is mounted, and a capacitor layer is formed therebeneath, which means that capacitors are connected through vias that pass through several insulation layers. Therefore, there is apprehension that the inductances of the vias adversely affect the intended stabilization of the power supply.